Generally, in a MOS transistor, the source region or the drain region is formed in an opposite-conductivity-type well included in a device region. In this case, the source region or the drain region is isolated from the well by the PN junction formed between the source region and the well or between the drain region and the well.
However, in the MOS transistor having such a general structure, the operation speed may be reduced due the parasitic capacity of the PN junction, and a leakage current may occur.
To resolve the problem, there has been proposed a MOS transistor structure in which in the device region, the well is isolated from the source region or the drain region by an isolation structure using an oxide film, a nitride film, and a void (space) locally formed under the source region or the drain region. Such MOS transistor structure may be importance because it may be effective to reduce the junction capacitance and the leakage current.
As a forming process of forming the MOS transistor structure, for example, Japanese Laid-open Patent Publication No. 2007-27231 (hereinafter “Patent Document 1”) discloses a method in which a laminated structure is formed in which a Si layer is formed on a Si—Ge mixed crystal layer, and then, only the Si—Ge mixed crystal layer is removed by using the etching-rate difference between the Si layer and the Si—Ge mixed crystal layer.
By filling the void (air hole) with a silicon oxide film the void being generated by removing the Si—Ge mixed crystal layer, it may become possible to locally form an embedded region where a silicon oxide film is locally embedded into under the source region or the drain region, so that so-called an SOI (Silicon-on-insulator) structure may locally be formed.